Verilog continuous assignment equivalent of always block -

how block replaced continuous assignment statement using ‘{ }’ , ‘? :’?

module mux16to8 (input [7:0] secsa, minsa, secsb, minsb, output reg [7:0] secs, mins, input sela, selb, hold, seldisp, output reg leda, ledb); @(*) begin     if (hold == 1'b1)        if (seldisp == 1'b1) begin         secs = secsa;         mins = minsa;         leda = 1'b0;         ledb = 1'b1;        end else begin          secs = secsb;          mins = minsb;          leda = 1'b1;          ledb = 1'b0;     end     else         if (sela == 1'b1) begin          secs = secsa;          mins = minsa;          leda = 1'b0;           ledb = 1'b1;         end else if (selb == 1'b1) begin            secs = secsb;            mins = minsb;            leda = 1'b1;            ledb = 1'b0;           end else begin            secs = 0;           mins = 0;          leda = 1'b1;          ledb = 1'b1;             end      end endmodule 

i thought @

assign secs={seldisp?{hold?1:0}:0}?secsa:secsb assign mins={seldisp?{hold?1:0}:0}?minsa:minsb.. 

i know not enough because secs , mins variables in loop, continous assignment should similar loop , right don't know if statements fine.

one solution this:

module mux16to8 (input [7:0] secsa, minsa, secsb, minsb, output [7:0] secs, mins, input sela, selb, hold, seldisp, output leda, ledb);  assign {secs, mins, leda, ledb} =     hold ? seldisp ? {secsa, minsa, 1'b0, 1'b1} :                      {secsb, minsb, 1'b1, 1'b0} :               sela ? {secsa, minsa, 1'b0, 1'b1} :               selb ? {secsb, minsb, 1'b1, 1'b0} :                      { 8'd0,  8'd0, 1'b1, 1'b1};  endmodule 

i've used following yosys script prove formal equivalence:

read_verilog q22998917a.v rename mux16to8 mux16to8_orig  read_verilog q22998917b.v  proc; opt miter -equiv mux16to8_orig mux16to8 miter flatten miter;;  sat -prove trigger 0 miter