using variable in for loop to specify index of an array in verilog -

i newbie in verilog. variables can not assigned index of array, how can code 1 in verilog, no compilation error occur?

module strmatch();  reg [15:0]str; integer i;  reg [10*8-1:0]searchbuffer;  initial begin str = "ab"; searchbuffer = "qwertabjkl";  (i=10;i>=2;i++)     begin    if(searchbuffer[(8*i-1:8*(i-2)]==str[15:0])        begin            $display("i");        end     end // end of end // end of initial  endmodule 

firstly have bracket in if statement causing syntax error. after fixing code still incorrect since you're using i on both sides of bit selection.

if you're taking slice, one of indices has constant. verilog has special notation taking constant range:

if (searchbuffer[8*i+:16]==str[15:0]) 

this use 8*i base , take slice of 16 bits. working example on eda playground.

note there - bit select:

  reg [15:0] big_vect;    reg [0:15] little_vect;     big_vect[lsb_base_expr    +: width_expr]    little_vect[msb_base_expr +: width_expr]     big_vect[msb_base_expr    -: width_expr]    little_vect[lsb_base_expr -: width_expr]