verilog - How does undefined input affect the selection? -


i writing verilog file. using following code function multiplexer:

assign out = raddr_mux ? a:b

however, output wave seems strange. enter image description here

as can see @ lower part of image, red line indicates raddr_mux not defined. however, sometimes, output out got value, output out has nothing. wondering how undefined affect selection behavior. thank you!

an x on input means undefined, is either 0 or 1.

if both inputs mux @ same value not matter select value is, output still defined has 1 of inputs. in our example select x both inputs , output 0, 4 5.

if inputs not same, output x, undefined either of input values.


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